It is the purpose of timing recovery to convert an asynchronously sampled read-out signal to a baud rate synchronous signal, which e.g. is used for bit detection, runlength limited decoding or joint bit detection and runlength limited decoding or subsequent channel decoding. A fully digital implementation of timing recovery control loop using a technique known as interpolated timing recovery abbreviated as ITR already has been disclosed by P. Kovintavewat et al, “Interpolated timing recovery”, in CRC Handbook of Coding and Signal Processing for Magnetic Recording Systems, pp. 27-1-27-16, 2005 as shown in FIG. 1.
With increased density, magnetic and optical storage systems exhibit high intersymbol interference and low signal to noise ratios, which makes timing recovery more challenging. Associated with increased intersymbol interference and decreased signal to noise ratios, the probability of cycle slips increases, i.e. samples after the timing recovery are shifted as ideal samples to the left or to the right by one or multiple bits. Due to loss of bit synchronization, cycle slips result in burst errors. A cycle slip detector and phase locked loop circuit and digital signal reproducing apparatus using the same already have been disclosed in U.S. Pat. No. 5,790,613A1. Zero-crossings of the read-out signal are employed for phase error detection to estimate timing phase errors and to detect cycle slips by examining two adjacent zero-crossings. However, zero-crossing based timing recovery is expected to perform poor under intersymbol interference and low signal to noise ratio conditions, because zero-crossings of the read-out signal do not provide reliable timing information under such conditions. Moreover, two adjacent instantaneous timing errors are compared to fixed thresholds in order to detect cycle slips, which may be sensitive to erroneously estimated timing error and may result in false alarms in the presence of frequency offset.
Furthermore, cycle slip detection using low pass filtering already has been disclosed by Thuringer in U.S. Pat. No. 6,973,150 B1. A phase detector output and a filtered phase difference compared to a threshold are used for cycle slip detection. An analog phase-locked loop with two carriers and an analog phase detector are used to determine a phase difference. A simple approach to detect cycle slips was proposed in A. Nayak's dissertation “Iterative Timing Recovery for Magnetic Recording Channels with Low Signal-to-Noise Ratio,” page 139, 2004. Specifically, if the difference between the currently estimated timing error and its delayed version is larger than a fixed threshold, then a cycle slip is detected. Wrongly estimated timing errors result in false detection of cycle slips. Moreover, frequency offsets may also cause false alarms.